1. Field
Integrated circuit packaging.
2. Description of Related Art
In an effort to improve interconnect speed, decrease power consumption and reduce integrated circuit package form factor, three-dimensional packages with die-to-die stacking has been promoted.
Die-to-die stack minimizes the effort to place all technologies on to a single die. Instead, multiple dies may be stacked together. Such dies may allow a different fabrication technology optimized for a particular type of circuitry, such as memory, logic, analog and sensors. Wide I/O memory is a recent dynamic random access memory (DRAM) technology that contemplates a memory die stacked on a microprocessor die or vice versa. JEDEC standard JESD229, “Wide I/O Single Data Rate,” December 2011, specifies four 128-bit channels, providing a 512-bit interface to DRAM. An interface between the dice involves, in one embodiment, solder connections.
In three-dimensional packaging, the assembly process flow depends on different variables, including package architecture (e.g., die size, substrate layout, etc.); fabrication materials and processes (e.g., silicon, back end of line (BEOL) metallization, die back side metallization, nitride stress); assembly materials and processes; and costs. The shape/topography of a chip during assembly is complex. Depending on the process flow variables, the chip or die shape can be concave, convex, saddle or other shape. During die-to-die bonding, the shape of one or both dies can effect the contact between the die dice and incompatible shapes can induce non-contact open, stretch solder joints and other defects that can induce process yield loss and reliability degradation.